Fallaes Communes de Inversores et Solutiones

1. Errōr praevalidī flūctus

Errōr praevalidī flūctus est ūnus ex fāciliōribus errōribus quos in operātiōne inverteris obviamur. Ut inverterem melius tueātur, saepe multiformis protectiōnis contra praevalidum flūctum implementātur. Ex grāvitāte praevalidī flūctus, hīc dīvidī potest in sequentia casūs: praevalidus flūctus modulī potentiae, praevalidus flūctus hardware, et praevalidus flūctus software. Saepe, praevalidus flūctus modulī potentiae est summum nivēlis errōris. Līmitātio praevalidī flūctus hardware est valdē minor quam līmitātio praevalidī flūctus modulī potentiae sed maior quam līmitātio praevalidī flūctus software. In celeritāte responsionis, obstructiō hardware est velox quam software.

Mechanismus reportandī ​praevalidī flūctus modulī potentiae​ est generaliter sīcut sequitur: Dēsignātiō hardware trāhit signum FAULT in primāriā laterā optocouploris ut commūtet cum IGBT conductionis flūctus valdē superat līmitātio praevalidī flūctus hardware (generaliter non plus quam 6 vices IGBT rated current). Circuitus hardware tunc obstructs PWM wave output et simul transmittit hoc signum ad pin control chip. Software respondet ad hoc signum per interrupt, statim claudens et obstructa faciens ulteriorem operātiōnem.

Mechanismus reportandī ​praevalidī flūctus hardware​ est generaliter sīcut sequitur: Uti circuitu comparātoris hardware, cum flūctus superat līmitātio praevalidī flūctus hardware detectatur, circuitus hardware obstructs PWM wave output et transmittit signum fault ad pin control chip. Software respondet per interrupt, statim claudens.

Mechanismus reportandī ​praevalidī flūctus software​ est generaliter sīcut sequitur: Post sampling trium phasium flūctuum, software calculat RMS valorem. Hic RMS valor comparatur ad līmitātio praevalidī flūctus software. Si superat līmitātio, praevalidus flūctus software reportatur, et inverter clauditur.

Generaliter, diagnōsis et resolutiō errōris praevalidī flūctus possunt implicāre sequentes passus:

1. Si inverter normaliter operābātur et raro reportabat praevalidum flūctum modulī potentiae, primum tenta reset erroris. Si reset fallit, modulī potentiae fortasse dāmnum est et requiritur repositiō.
2. Si reset succedit, considera si conditiōnēs operātionis mutātae sunt (exemplī grātiā, momentanea supercārus/cessātiō causāns subitum flūctum magnam). Si causāta ab externā anomalī, eliminā causam ut stabilem operātionem servēs. Si mūtātiō intencionalis (exemplī grātiā, auctus demandae oneris aut impactus oneris), redige flūctus magnos per extensam tempus accelerātiōnis, adjusta speed/current loop PI parametrōs ut optimizēs performantiam contrōl, aut enable overcurrent stall prevention function.
3. Si reset succedit sine mūtātiōnibus externīs, inspice circuitum output inverter pro terrārum fault vel short circuits. Elimina quod invēneris. Si nullum existit, observa magnitudinem flūctus per totum cyclum operātionis. Si stabilis sine significativis surges, considera interfectiōnem electricā et inspecta cablātiō/terrārum.
4. Durante commissioning, si errōres praevalidī flūctus facile occurrunt, primum verificā correctam setting inverter et motor parametrōs, includens matching inverter et motor power ratings. Si settings sunt correctae et power est matched sed errōr persistit, fac dynamic parameter identification ut assecurāris accurātiam motor parametrōrum.
5. Si praevalidus flūctus occurrat durante startup sub V/f control, inspecta si torque boost setting est nimis alta et reduca si necessarium. Inspecta quoque si V/f curve settings sunt irrationabilis et adjusta secundum.
6. Si incipit dum motor liberē versātur, praevalidus flūctus fortasse occurrat. Expecta donec motor totaliter cessāverit antequam incipias, aut set starting method to flying start / spin tracking start.

​II. Errōr praevalidae voltūs​

Praevalidus voltus est item unum ex communioribus errōribus inverter. Ut inverter tueātur, saepe multiformis protectiōnis contra praevalidam voltum implementātur. Ex grāvitāte, generaliter dīviditur in hardware praevalidam voltum et software praevalidam voltum.

Typice, līmitātio praevalidae voltūs hardware est altior quam līmitātio praevalidae voltūs software, et obstructiō hardware est velox. Mechanismus reportandī ​praevalidae voltūs hardware​ est generaliter: Uti circuitu comparātoris hardware, cum DC bus voltage superat līmitātio hardware, circuitus hardware obstructs PWM output et signālit control chip. Software respondet per interrupt, claudens.

Mechanismus reportandī ​praevalidae voltūs software​ est generaliter: Post sampling DC bus voltage, software comparat ad līmitātio software. Si superat, praevalida volta software reportatur, et inverter clauditur.

Diagnōsis et resolutiō errōris praevalidae voltūs typice implicat:

1. Si significativa energia regenerātur ad grid, inspecta si braking resistor unit (BRU) est installāta et aptē magnitūdinis.
2. Si regenerāta energia modesta est, tenta extendere tempus decelerātiōnis ut reducas regeneration, aut adjusta speed/current loop PI parametrōs ut meliores performantiam contrōl.
3. Si modesta regeneratio cum momentanis spikes voltūs occurrat (exemplī grātiā, subita amissio oneris magni) et stopping position/time non critica est, enable overvoltage stall prevention function. Ut cum cautelā quia posset impedire tempestivam cessationem; ne utāre ubi stopping position est critica.
4. Si regenerāta energia valde parva est, inspecta si tres phasium input voltage nimis alta est.
5. Inspecta si motor agitur ab externā vi (exemplī grātiā, overhauling load). Si sic, elimina hanc vim.

​III. Amīssio phasīs input​

Amīssio phasīs input est alius relativē communis errōris inverter. Mechanismi reportandi variānt per manufactorēs/modellos sed generaliter cadunt in duōs typōs:

1. Detection per software: Duō line voltages sampleantur et convertuntur in phasīs voltūs. Phase unbalance calculatur ut determinet an amīssio phasīs conditiones impleat.
2. Detection per hardware: Circuitus dedicātus detectat amīssionem phasīs et signālit control chip per pin. Software monitorat status huius pin ut determinet amīssionem phasīs.

Si amīssio phasīs detectatur, errōris reportatur, et inverter clauditur (vel generat alarmam in aliquibus casibus).

Diagnōsis et resolutiō usualiter implicat:

1. Inspecta integritātem et securitātem trium phasium input power connections.
2. Verificā ut omnes input power phases sint praesentes (nullae fuses ruptae, breakers tripped).
3. Si utrumque 1 & 2 confirmāta sunt OK, monitora input power et inspecta logicam contrōl pro quālibet automatic disconnection/reconnection sequences.

​IV. Inverter Overload​

Inverter overload est occasionaliter reportatus errōris. Mechanismi reportandi variānt sed generaliter sunt:

1. ​Thermal accumulation method:​​ Software calculat thermal accumulation value basēs current (et possibiliter aliīs factoribus) per tempus, comparans ad design threshold. Superando threshold triggerat overload errōris et shutdown.
2. ​Inverse-time characteristic:​​ Basēs inverter's designed overload curvā, software calculat quantom tempus specific overcurrent magnitude permittitur. Timing incipit quando overcurrent occurrit; superando permittitum tempus triggerat errōris et shutdown.

Diagnōsis et resolutiō typicaliter implicat:

1. Inspecta si load's duty cycle (ON/OFF times) adheret ad inverter's overload curvā. Adjusta aut reduce load current ut prohibeas superare duration limits curvā.
2. Inspecta si motor power superat inverter's continuous load rating. Si load vere magnus, selecta higher-power inverter.

​V. Motor Stall​

Motor stall est alius occasionaliter reportatus errōris inverter. Essentialiter, inverter iubet motorem attingere certam velocitātem et emit significativam torque, sed motor non versātur recte, permanens in stantibus conditiōnibus.

Conditiones typically required to trigger a motor stall errōris:

1. The feedback torque current exceeds the set stall current threshold and this condition lasts longer than the set stall time.
2. During this period, the actual motor speed is below the set stall frequency threshold.
3. The inverter is not operating in V/f control mode (since V/f lacks speed feedback, stall detection isn't possible).

Troubleshooting and resolving motor stall faults generally involve:

1. Check if an external force physically prevents motor rotation. Eliminate the cause.
2. Adjust the stall frequency and stall current threshold parameters according to the application's needs.
3. Check if the motor/load power exceeds the inverter's capability. If so, select an appropriately sized inverter.