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Free Expert Guides on Power Systems, Circuit Design & Electrical Troubleshooting

Access free engineering resources from IEE Business—covering power design, circuit layout, equipment selection, and troubleshooting. Expert-developed guides help engineers, procurement, and project teams make better decisions. Stay ahead on smart grids, renewables, efficiency, and AI tools. Improve reliability, reduce downtime, and enhance outcomes with real-world solutions. Explore our knowledge hub today.
Data-driven next-generation smart grid towards sustainable energy evolution: techniques and technology review
This paper exhibits the conceptual framework of NGSG by enabling some intelligent technical features to ensure its reliable operation, including intelligent control, agent-based energy conversion, edge computing for energy management, internet of things (loT) enabled inverter, agent-oriented demand side management, etc. Also, a study on the development of data-driven NGSG is discussed to facilitate the use of emerging data-driven techniques (DDTs) for the sustainable operation of the SG.1.Intr
03/07/2024
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The workflow of the automated extraction tool for simplified EKV parameters
The increasing demand for high performance and energy efficiency in Artificial Neural Networks (ANNs) accelerators has driven a wide range of application-specific integrated circuits (ASICs). Besides, the rapid deployment of low-power IoT devices requires highly efficient computing, which as a result urges the need to explore low-power hardware implementations in different domains. This paper proposes a spatially unrolled time-domain accelerator that uses an ultra-low-power digital-to-time conve
03/06/2024
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A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier
In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architec
03/06/2024
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